A design for testability scheme with applications to data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Area-efficient fault detection during self-recovering microarchitecture synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
Behavioral Synthesis for Easy Testability in Data Path Allocation
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Area-efficient fault detection during self-recovering microarchitecture synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
A controller-based design-for-testability technique for controller-data path circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Introspection: a low overhead binding technique during self-diagnosing microarchitecture synthesis
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Behavioral Testability Insertion for Datapath/Controller Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Improving Testability of Non-Scan Designs during BehavioralSynthesis
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
A scheme for integrated controller-datapath fault testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems
Journal of Electronic Testing: Theory and Applications
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Allocation Techniques for Reducing BIST Area Overhead ofData Paths
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
High-Level Test Synthesis for Behavioral and Structural Designs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Fast and accurate estimation of floorplans in logic/high-level synthesis
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Built-in Self Test Based on Multiple On-Chip Signature Checking
Journal of Electronic Testing: Theory and Applications
Scheduling and module assignment for reducing BIST resources
Proceedings of the conference on Design, automation and test in Europe
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
Journal of Electronic Testing: Theory and Applications
Automatic Synthesis of Self-Recovering VLSI Systems
IEEE Transactions on Computers
Test session oriented built-in self-testable data path synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Structural BIST Insertion Using Behavioral Test Analysis
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An RTL Methodology to Enable Low Overhead Combinational Testing
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
ETW '00 Proceedings of the IEEE European Test Workshop
BISTing Data Paths at Behavioral Level
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Addressing Early Design-For-Test Synthesis in a Production Environment
ITC '97 Proceedings of the 1997 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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