A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis

Authors:
D. Berthelot;M. L. Flottes;B. Rouzeyre
Affiliations:
Laboratoire d'Informatique, de Robotique et de Micro-Electronique de Montpellier, U.M.R. 5506 CNRS/Université de Montpellier 2, 161 rue Ada, 34392 Montpellier Cedex 5, France;Laboratoire d'Informatique, de Robotique et de Micro-Electronique de Montpellier, U.M.R. 5506 CNRS/Université de Montpellier 2, 161 rue Ada, 34392 Montpellier Cedex 5, France;Laboratoire d'Informatique, de Robotique et de Micro-Electronique de Montpellier, U.M.R. 5506 CNRS/Université de Montpellier 2, 161 rue Ada, 34392 Montpellier Cedex 5, France
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2001

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Abstract

This paper presents a partitioned and embedded BIST technique for data path like circuits. The BIST scheme is defined at behavioral level for full optimization of both system and BIST modes during High Level Synthesis. Test time, area overhead and fault coverage are under the scope of the method. User-given constraints on fault coverage to achieve on data path operators and on test time are used to guide the BIST insertion technique towards the lowest area overhead solution.