Efficient BIST hardware insertion with low test application time for synthesized data paths
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Partial BIST insertion to eliminate data correlation
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
Journal of Electronic Testing: Theory and Applications
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
ETW '00 Proceedings of the IEEE European Test Workshop
Degree-Of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
BISTing Data Paths at Behavioral Level
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A study of hardware design and overhead in Built-in-Self-Testable UART
WISICT '04 Proceedings of the winter international synposium on Information and communication technologies
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data
Journal of Electronic Testing: Theory and Applications
Fast Computation of Data Correlation Using BDDs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.03 |
Implementing a built-in self-test by a “test per clock” scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a scheme is implemented by test registers, for instance built-in logic block observers (BILBO's) and concurrent BILBO's (CBILBO's), which are inserted into the circuit structure at appropriate places. An algorithm is presented which is able to find the cost optimal placement of test registers for nearly all the ISCAS'89 sequential benchmark circuits, and a suboptimal solution with slightly higher costs is obtained for all the circuits within a few minutes of computing time. The algorithm can also be applied to the Minimum Feedback Vertex Set problem in partial scan design, and an optimal solution is found for all the benchmark circuits. The provably optimal solutions for the benchmark circuits mainly use CBILBO's which can simultaneously generate test patterns and compact test responses. Hence, test scheduling is not required, test control is simplified, and test application time is reduced