Degree-Of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area

Authors:
Samir Roy;Biplab K. Sikdar;Monalisa Mukherjee;Debesh K. Das
Affiliations:
Department of Computer Science & Technology, Kalyani Govt. Engineering College, Kalyani, India;Department of Computer Science & Technology , Bengal Engineering College (D U), Howrah, India;Department of Computer Science & Technology , Bengal Engineering College (D U), Howrah, India;Department of Computer Science & Engineering, Jadavpur University, Calcutta, India 7
Venue:
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Year:
2002

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Abstract

This paper reports the design of BIST structures for sequential machines. Testability of an FSM is limited due to the fact that some machine states remain unreachable and some act as a sink under any input sequence. The proposed scheme provides uniform mobility, referred to as degree of freedom, among the machine states in test mode by enhancing the reachability and emitability of the states. Uniform mobility of states ensures higher fault efficiency in a BIST structure. A graph based approach is introduced for state code assignment to minimize gate area. Experimental results on benchmark circuits establish that the proposed scheme does improve the BIST quality simultaneously reducing the gate area of the synthesized machine.