Improved Built-In Test Pattern Generators Based on Comparison Units for Synchronous Sequential Circuits

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ICCD '98 Proceedings of the International Conference on Computer Design
Year:
1998

Citing 0
Cited 4

Degree-Of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines

VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area

Journal of Electronic Testing: Theory and Applications
Efficient BIST design for sequential machines using FiF-FoF values in machine states

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

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Abstract

Using highly optimized, custom circuits and fast dynamic array control structures, a small team of designers at the IBM Austin Research Laboratory has developed a one gigahertz microprocessor. This paper describes the custom datapath circuit technology ...