Built-in test generation for synchronous sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Degree-Of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
ICCD '98 Proceedings of the International Conference on Computer Design
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper introduces a novel BIST-quality metric termed as the FiF -- FoF (Fan-in-Factor & Fan-out-Factor) defined on FSM-states. Based on the FiF -- FoF analysis, an efficient scheme is presented that ensures all state codes appear with uniform likelyhood at the present state (PS) lines during the test phase. This results in higher fault efficiency in a BIST structure. Experimental results on MCNC benchmarks show that the scheme improves fault efficiency of sequential circuits significantly, with marginal area overhead.