Built-In Testing of Memory Using an On-Chip Compact Testing Scheme
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A method for generating weighted random test pattern
IBM Journal of Research and Development
An overview of deterministic functional RAM chip testing
ACM Computing Surveys (CSUR)
IBM Journal of Research and Development
Design considerations for parallel pseudorandom pattern generators
Journal of Electronic Testing: Theory and Applications
Cellular automata circuits for built-in self test
IBM Journal of Research and Development
BIDES: a BIST design expert system
Journal of Electronic Testing: Theory and Applications
The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
Automated BIST for Sequential Logic Synthesis
IEEE Design & Test
Realistic Built-In Self-Test for Static RAMs
IEEE Design & Test
A Testability Strategy for Microprocessor Architecture
IEEE Design & Test
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
Built-in test generation for synchronous sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Random Pattern Testability of Memory Control Logic
IEEE Transactions on Computers
Test Data Decompression for Multiple Scan Designs with Boundary Scan
IEEE Transactions on Computers
An IEEE 1149.1 Compliant Test Control Architecture
Journal of Electronic Testing: Theory and Applications
Efficient BIST hardware insertion with low test application time for synthesized data paths
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Improving the test quality for scan-based BIST using a general test application scheme
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A testability metric for path delay faults and its application
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Random limited-scan to improve random pattern testing of scan circuits
Proceedings of the 38th annual Design Automation Conference
Generating efficient tests for continuous scan
Proceedings of the 38th annual Design Automation Conference
Testing Schemes for FIR Filter Structures
IEEE Transactions on Computers
Effective diagnostics through interval unloads in a BIST environment
Proceedings of the 39th annual Design Automation Conference
On output response compression in the presence of unknown output values
Proceedings of the 39th annual Design Automation Conference
Improving the proportion of at-speed tests in scan BIST
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment
Journal of Electronic Testing: Theory and Applications
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
Design for Testability in Hardware-Software Systems
IEEE Design & Test
A novel test methodology for core-based system LSIs and a testing time minimization problem
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An almost full-scan BIST solution-higher fault coverage and shorter test application time
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Fault Scanner for Reconfigurable Logic
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Multiplicative Window Generators of Pseudo-random Test Vectors
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Novel BIST Architecture With Built-in Self Check
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Degree-Of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Bridging the Gap Between Embedded Test and ATE
ITC '00 Proceedings of the 2000 IEEE International Test Conference
DESIGN OF COMPACTORS FOR SIGNATURE-ANALYZERS IN BUILT-IN SELF-TEST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Highly-Efficient Transparent Online Memory Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
FAULT DIAGNOSIS IN-SCAN-BASED BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Parameterizable Testing Scheme for FIR Filters
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Test Width Compression for Built-In Self Testing
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Emulating static faults using a Xilinx based emulator
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units
IEEE Transactions on Computers
Test-decompression mechanism using a variable-length multiple-polynomial LFSR
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor
Journal of Electronic Testing: Theory and Applications
Scan-BIST based on transition probabilities
Proceedings of the 41st annual Design Automation Conference
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Journal of Electronic Testing: Theory and Applications
Efficient BIST design for sequential machines using FiF-FoF values in machine states
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Increasing embedding probabilities of RPRPs in RIN based BIST
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
| Hi-index | 0.01 |
For pt.1 see ibid., vol.10, no.1, p.73-82 (1993). The hardware structures and tools used to implement built-in self-test (BIST) pattern generation and response analysis concepts are reviewed. The authors describe testing approaches for general and structured logic, including ROMs, RAMs, and PLAs. They illustrate BIST techniques with real-world examples.