Increasing embedding probabilities of RPRPs in RIN based BIST

Authors:
Dong-Sup Song;Sungho Kang
Affiliations:
Dept. of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea;Dept. of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea
Venue:
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2005

Citing 11
Cited 0

Built-in test for VLSI: pseudorandom techniques

Built-in test for VLSI: pseudorandom techniques
A method for generating weighted random test pattern

IBM Journal of Research and Development
Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers

IEEE Transactions on Computers - Special issue on fault-tolerant computing
Bit-flipping BIST

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A Tutorial on Built-in Self-Test. I. Principles

IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications

IEEE Design & Test
Using BIST Control for Pattern Generation

Proceedings of the IEEE International Test Conference
Test vector encoding using partial LFSR reseeding

Proceedings of the IEEE International Test Conference 2001
A ROMless LFSR Reseeding Scheme for Scan-based BIST

ATS '02 Proceedings of the 11th Asian Test Symposium
Test-decompression mechanism using a variable-length multiple-polynomial LFSR

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test set embedding for deterministic BIST using a reconfigurable interconnection network

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we propose a new clustered reconfigurable interconnect network (CRIN) BIST to improve the embedding probabilities of random-pattern-resistant-patterns. The proposed method uses a scan-cell reordering technique based on the signal probabilities of given test cubes and specific hardware blocks that increases the embedding probabilities of care bit clustered scan chain test cubes. We have developed a simulated annealing based algorithm that maximizes the embedding probabilities of scan chain test cubes to reorder scan cells, and an iterative algorithm for synthesizing the CRIN hardware. Experimental results demonstrate that the proposed CRIN BIST technique achieves complete fault coverage with lower storage requirement and shorter testing time in comparison with a previous method.