Linear Dependencies in Linear Feedback Shift Registers
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Design considerations for parallel pseudorandom pattern generators
Journal of Electronic Testing: Theory and Applications
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
On Linear Dependencies in Subspaces of LFSR-Generated Sequences
IEEE Transactions on Computers
STARBIST: scan autocorrelated random pattern generation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Mixed-Mode BIST Using Embedded Processors
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Test Data Decompression for Multiple Scan Designs with Boundary Scan
IEEE Transactions on Computers
A Method for Designing a Deterministic Test Pattern Generator Based on Cellular Automata
Journal of Electronic Testing: Theory and Applications
Minimized Power Consumption for Scan-Based BIST
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 14th international symposium on Systems synthesis
FPGA test time reduction through a novel interconnect testing scheme
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
A mixed-mode BIST scheme based on folding compression
Journal of Computer Science and Technology
A Unified DFT Approach for BIST and External Test
Journal of Electronic Testing: Theory and Applications
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
Journal of Electronic Testing: Theory and Applications
An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment
Journal of Electronic Testing: Theory and Applications
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
Journal of Electronic Testing: Theory and Applications
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
IEEE Design & Test
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
An algorithmic approach to optimizing fault coverage for BIST logic synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A highly regular multi-phase reseeding technique for scan-based BIST
Proceedings of the 13th ACM Great Lakes symposium on VLSI
LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds
Journal of Electronic Testing: Theory and Applications
Fast seed computation for reseeding shift register in test pattern compression
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Seed encoding with LFSRs and cellular automata
Proceedings of the 40th annual Design Automation Conference
Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
Test application time and volume compression through seed overlapping
Proceedings of the 40th annual Design Automation Conference
Methods to reduce test application time for accumulator-based self-test
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Deterministic Partitioning Techniques for Fault Diagnosis in Scan-Based BIST
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Vector Encodin Usin Partial LFSR Reseedin
ITC '01 Proceedings of the 2001 IEEE International Test Conference
TWO-DIMENSIONAL TEST DATA COMPRESSION FOR SCAN-BASED DETERMINISTIC BIST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Scan Encoded Test Pattern Generation for BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
On Using Machine Learning for Logic BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Test Width Compression for Built-In Self Testing
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing
IEEE Design & Test
On test data volume reduction for multiple scan chain designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multimode scan: Test per clock BIST for IP cores
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computers
Test-decompression mechanism using a variable-length multiple-polynomial LFSR
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor
Journal of Electronic Testing: Theory and Applications
Scalable Delay Fault BIST for Use with Low-Cost ATE
Journal of Electronic Testing: Theory and Applications
Challenges and directions for testing IC
Integration, the VLSI Journal
Logic BIST Using Constrained Scan Cells
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Combining dictionary coding and LFSR reseeding for test data compression
Proceedings of the 41st annual Design Automation Conference
Achieving high encoding efficiency with partial dynamic LFSR reseeding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test data compression technique for embedded cores using virtual scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Evolutionary Optimization in Code-Based Test Compression
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Scan test planning for power reduction
Proceedings of the 44th annual Design Automation Conference
A BIST TPG for low power dissipation and high fault coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GECOM: test data compression combined with all unknown response masking
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Journal of Electronic Testing: Theory and Applications
State skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores
Proceedings of the conference on Design, automation and test in Europe
Randomness quality of permuted pseudorandom binary sequences
Mathematics and Computers in Simulation
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Deviation-based LFSR reseeding for test-data compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Genetic algorithm for test pattern generator design
Applied Intelligence
A New Built-in TPG Based on Berlekamp---Massey Algorithm
Journal of Electronic Testing: Theory and Applications
BISD: scan-based built-in self-diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
A diagnosis algorithm for extreme space compaction
Proceedings of the Conference on Design, Automation and Test in Europe
Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects
Proceedings of the Conference on Design, Automation and Test in Europe
Analysis and improvement of a pseudorandom number generator for EPC Gen2 tags
FC'10 Proceedings of the 14th international conference on Financial cryptograpy and data security
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns
Journal of Electronic Testing: Theory and Applications
Correlation-based rectangular encoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression using selective encoding of scan slices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new scheme of test data compression based on equal-run-length coding (ERLC)
Integration, the VLSI Journal
Increasing embedding probabilities of RPRPs in RIN based BIST
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
LFSR seed computation and reduction using SMT-based fault-chaining
Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we propose a new scheme for Built-In Test (BIT) that uses Multiple-polynomial Linear Feedback Shift Registers (MP-LFSR's). The same MP-LFSR that generates random patterns to cover easy to test faults is loaded with seeds to generate deterministic vectors for difficult to test faults. The seeds are obtained by solving systems of linear equations involving the seed variables for the positions where the test cubes have specified values. We demonstrate that MP-LFSR's produce sequences with significantly reduced probability of linear dependence compared to single polynomial LFSR's. We present a general method to determine the probability of encoding as a function of the number of specified bits in the test cube, the length of the LFSR and the number of polynomials. Theoretical analysis and experiments show that the probability of encoding a test cube with $s$ specified bits in an $s$-stage LFSR with 16 polynomials is 1驴10$^{-6}.$ We then present the new BIT scheme that allows for an efficient encoding of the entire test set. Here the seeds are grouped according to the polynomial they use and an implicit polynomial identification reduces the number of extra bits per seed to one bit. The paper also shows methods of processing the entire test set consisting of test cubes with varied number of specified bits. Experimental results show the tradeoffs between test data storage and test application time while maintaining complete fault coverage.Index Terms驴Built-In Test, hardware test pattern generators, input test data compression and decompression, multiple-polynomial LFSR, reseeding, scan design.