Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
On computing optimized input probabilities for random tests
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A method for generating weighted random test pattern
IBM Journal of Research and Development
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Structured Logic Testing
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
A Multiple Seed Linear Feedback Shift Register
IEEE Transactions on Computers
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
MFBIST: A BIST Method for Random Pattern Resistant Circuits
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Calculatoin of Multiple Sets of Weights for Weighted-Random Testing
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
BIST hardware generator for mixed test scheme
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Decompression of test data using variable-length seed LFSRs
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Transformed pseudo-random patterns for BIST
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A novel pattern generator for near-perfect fault-coverage
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
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This paper presents a new approach for designing testsequences to be generated on-chip. The proposedtechnique is based on machine learning, and provides a wayto generate efficient patterns to be used during BIST testpattern generation. The main idea is that test patternsdetecting random pattern resistant faults are not embeddedin a pseudo-random sequence as in existing techniques, butrather are used to produce relevant features allowing togenerate directed random test patterns that detect randompattern resistant faults as well as easy-to-test faults. A BISTimplementation that uses a classical LFSR plus a smallamount of mapping logic is also proposed in this paper.Results are shown for benchmark circuits which indicatethat our technique can reduce the weighted orpseudo-random test length required for a particular faultcoverage. Other results are given to show the possible tradeoff between hardware overhead and test sequence length.An encouraging point is that results presented in this paper,although they are comparable with those of existingmixed-mode techniques, have been obtained with amachine learning tool not specifically developed for BISTgeneration and therefore may significantly be improved.