Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A Unified DFT Approach for BIST and External Test
Journal of Electronic Testing: Theory and Applications
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Ring Architecture Strategy for BIST Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
Characteristic faults and spectral information for logic BIST
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
On Using Machine Learning for Logic BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
On Using Deterministic Test Sets in BIST
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Testing strategies for networks on chip
Networks on chip
A BIST Pattern Generator Design for Near-Perfect Fault Coverage
IEEE Transactions on Computers
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor
Journal of Electronic Testing: Theory and Applications
Logic BIST Using Constrained Scan Cells
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST
IEEE Transactions on Computers
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Abstract: A new design methodology for a pattern generator is proposed, formulated in the context of on-chip BIST. The pattern generator consists of two components: a GLFSR, earlier proposed as a pseudo-random pattern generator, and combinational logic, to snap the outputs of the pseudo-random pattern generator. Using fewer test patterns with only a small area overhead, this combinatorial logic block, for a particular CUT, can be designed to achieve nearly 100% single stuck-at fault coverage. Specifically, where weighted pattern generators only enhance the probability of testing a specified set of hard-to-detect faults, the proposed combinational logic, using a comparable hardware overhead, can guarantee generating the test for those faults. Experimental results demonstrate that under identical conditions, the fault coverage of the proposed pattern generator is significantly higher, compared to the conventional weighted pattern generation techniques. For enhancing effectiveness, this combinational logic mapping technique can also be used to augment any weighted pattern technique. Because LFSRs are special cases of GLFSRs, our design is more general than LFSR-based designs.