Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Utilization of On-Line (Concurrent) Checkers during Built-In Self-Test and Vice Versa
IEEE Transactions on Computers
Shift Register Sequences
BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms
IEEE Transactions on Computers
BIST Generators for Sequential Faults
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Two-Pattern Test Capabilities of Autonomous TPG Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
BIST and Delay Fault Detection
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
GLFSR - A New Test Pattern Generator for Built-In Self-Test
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Accumulator-based BIST approach for stuck-open and delay fault testing
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A BIST approach to delay fault testing with reduced test length
EDTC '95 Proceedings of the 1995 European conference on Design and Test
BIST hardware generator for mixed test scheme
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Generating deterministic unordered test patterns with counters
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Transformed pseudo-random patterns for BIST
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A novel pattern generator for near-perfect fault-coverage
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
An Effective Multi-Chip BIST Scheme
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
An Accumulator-Based BIST Approach for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications
LFSR-Based Deterministic TPG for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Design for Delay Testability in High-Speed Digital ICs
Journal of Electronic Testing: Theory and Applications
Detection of CMOS address decoder open faults with March and pseudo random memory tests
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Bridging the Testing Speed Gap: Design for Delay Testability
ETW '00 Proceedings of the IEEE European Test Workshop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Many Built-in Self Test (BIST) pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs of patterns for delay faults testing with LFSRs. A new synthesis procedure for a n-size LFSR is given and guarantees that a deterministic set of n precomputed test pairs is embedded in the maximal length pseudo-random test sequence of the LFSR. Sufficient and necessary conditions for the synthesis of this pseudo-deterministic LFSR are provided and show that at-speed delay faults testing becomes a reality without any additional cost for the LFSR. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other technique proposed so far.