Cluster-cover: a theoretical framework for a class of VLSI-CAD optimization problems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Shift Register Sequences
BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms
IEEE Transactions on Computers
BIST Generators for Sequential Faults
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Two-Pattern Test Capabilities of Autonomous TPG Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
An algorithmic approach to optimizing fault coverage for BIST logic synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
BIST and Delay Fault Detection
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Exploiting BIST Approach for Two-Pattern Testing
ATS '98 Proceedings of the 7th Asian Test Symposium
Accumulator-based BIST approach for stuck-open and delay fault testing
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A BIST approach to delay fault testing with reduced test length
EDTC '95 Proceedings of the 1995 European conference on Design and Test
On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An optimized BIST test pattern generator for delay testing
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A mixed-mode BIST scheme based on folding compression
Journal of Computer Science and Technology
Accumulator-based pseudo-exhaustive two-pattern generation
Journal of Systems Architecture: the EUROMICRO Journal
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This paper proposes an approach to designing a cost-effective deterministic test pattern generator (TPG) for two-pattern testing. Given a set of pre-generated test-pair set (obtained by an ATPG tool) with a pre-determined (path delay) fault coverage, a simple TPG is synthesized to apply the given test-pair set in a minimal test time. To achieve this objective, a configurable linear feedback shift register (CLFSR) structure is used. Techniques are developed to synthesize such a TPG, which is used to generate an unordered deterministic test-pair set. The resulting TPG is efficient in terms of hardware size and speed performance. Experiments on benchmark circuits indicate that TPG designed using the proposed procedure obtain high path delay fault coverage in short test length.