Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Circular self-test path: a low-cost BIST technique
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Shift Register Sequences
BIST Generators for Sequential Faults
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
At-Speed Test is not Necessarily an AC Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Two-Pattern Test Capabilities of Autonomous TPG Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
BIST and Delay Fault Detection
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Error Control Coding, Second Edition
Error Control Coding, Second Edition
Distributed BIST Architecture to Combat Delay Faults
Journal of Electronic Testing: Theory and Applications
LFSR-Based Deterministic TPG for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Detection of CMOS address decoder open faults with March and pseudo random memory tests
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A BIST scheme for the detection of path-delay faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Scan Latch Design for Delay Test
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Scalable Delay Fault BIST for Use with Low-Cost ATE
Journal of Electronic Testing: Theory and Applications
Accumulator-based pseudo-exhaustive two-pattern generation
Journal of Systems Architecture: the EUROMICRO Journal
Recursive pseudo-exhaustive two-pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An effective two-pattern test generator for Arithmetic BIST
Computers and Electrical Engineering
| Hi-index | 14.99 |
Testing for delay and CMOS stuck-open faults requires two-pattern tests, and typically a large number of two pattern tests are needed. Built-in self-test (BIST) schemes are attractive for comprehensive testing of such faults. BIST test pattern generators (TPGs) for two-pattern testing, should be designed to ensure high transition coverage. In this paper, necessary and sufficient conditions to ensure complete/maximal transition coverage for linear feedback shift register (LFSR) and cellular automata (CA) have been derived. The theory developed here identifies all LFSR/CA TPGs that maximize transition coverage under any given TPG size constraint. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing. Also, CA are shown to be better TPGs than LFSRs for two pattern testing, independent of their feedback rules. Based on the necessary sufficient conditions, efficient algorithms to design optimal TPGs for two-pattern testing have been developed. Experiments on benchmark circuits indicate that TPGs designed using the procedures outlined in this paper obtain high robust path delay fault coverage in short test lengths.