Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
AC strength of a pattern generator
Journal of Electronic Testing: Theory and Applications
An efficient built-in self test method for robust path delay fault testing
Journal of Electronic Testing: Theory and Applications
Design methodology for IBM ASIC products
IBM Journal of Research and Development
Hierarchical Delay Test Generation
Journal of Electronic Testing: Theory and Applications
Delay Test Generation: A Hardware Perspective
Journal of Electronic Testing: Theory and Applications
Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Delay Fault Coverage Enhancement Using Variable Observation Times
Journal of Electronic Testing: Theory and Applications
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms
IEEE Transactions on Computers
Overview of PowerPCTM 620 Multiprocessor Verification Strategy
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Production Experience with Built-In Self-Test in the IBM ES/9000 System
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Scan Latch Design for Delay Test
Proceedings of the IEEE International Test Conference
Delay Testing with Clock Control: An Alternative to Enhanced Scan
Proceedings of the IEEE International Test Conference
Addressing Early Design-For-Test Synthesis in a Production Environment
Proceedings of the IEEE International Test Conference
Design for Primitive Delay Fault Testability
Proceedings of the IEEE International Test Conference
The PowerPC 603TM Microprocessor: An Array Built-In Self-Test Mechanism
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Generator choices for delay test
ATS '95 Proceedings of the 4th Asian Test Symposium
An effective BIST scheme for carry-save and carry-propagate array multipliers
ATS '95 Proceedings of the 4th Asian Test Symposium
An optimized BIST test pattern generator for delay testing
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Distributed Diagnosis of Interconnections in SoC and MCM Designs
Journal of Electronic Testing: Theory and Applications
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To successfully combat delay faults there is an urgent need for a proper design for testability (DFT). The foundation of any DFT methodology rests on its scan design. This paper describes three versions of a new design of a shift register latch that lend themselves to distributed self-test and delay test. The advantages of this new SRL is faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Adoption of this new DFT methodology brings us closer to the ideal target of one test-per-clock as opposed to one test-per-scan. Operation, cost, and other attributes are studied in detail. Results of adopting one of these SRLs are reported on ten pilot chips.