A hierarchical approach test vector generation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
On testing delay faults in macro-based combinational circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On path selection in combinational logic circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
Statistical methods for delay fault coverage analysis
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
An efficient automatic test generation system for path delay faults in combinational circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Distributed BIST Architecture to Combat Delay Faults
Journal of Electronic Testing: Theory and Applications
On theoretical and practical considerations of path selection for delay fault testing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Experience in critical path selection for deep sub-micron delay test and timing validation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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Delay testing is used to detect timing errors in a digital circuit.In this paper, we report a tool called MODET forautomatic test generation for path delay faults in modular combinational circuits. Our technique usesprecomputed robust delay tests for individual modules to computerobust delay tests for the module-level circuit. We present alongest path theorem at the module level ofabstraction which specifies the requirements for path selectionduring delay testing. Based on this theorem, we propose a pathselection procedure in module-level circuits and report efficientalgorithms for delay test generation. MODET hasbeen tested against a number of hierarchical circuits with impressivespeedups in relation to gate-level test generation.