Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
The interdependence between delay-optimization of synthesized networks and testing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Field-programmable gate arrays
Field-programmable gate arrays
Characterization of Boolean functions for rapid matching in FPGA technology mapping
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Application of Ternary Algebra to the Study of Static Hazards
Journal of the ACM (JACM)
Functional test generation for delay faults in combinational circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Hierarchical Delay Test Generation
Journal of Electronic Testing: Theory and Applications
Functional test generation for delay faults in combinational circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ATPG tools for delay faults at the functional level
DATE '99 Proceedings of the conference on Design, automation and test in Europe
ATPG tools for delay faults at the functional level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The coupling model for function and delay faults
Journal of Electronic Testing: Theory and Applications
Robust Coupling Delay Test Sets
Journal of Electronic Testing: Theory and Applications
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We consider the problem of testing for delay faults in macro-based circuits. Macro-based circuits are obtained as a result of technology mapping. Gate-level fault models cannot be used for such circuits, since the implementation of a macro may not have an accurate gate-level counterpart, or the macro implementation may not be known. Two delay fault models are proposed for macro-based circuits. The first model is analogous to the gate-level gross delay fault model. The second model is analogous to the gate-level path delay fault model. We provide fault simulation procedures, and present experimental results.