On testing delay faults in macro-based combinational circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Fastpath: A Path-Delay Test Generator for Standard Scan Designs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Functional test generation for delay faults in combinational circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ATPG tools for delay faults at the functional level
DATE '99 Proceedings of the conference on Design, automation and test in Europe
SATIRE: a new incremental satisfiability engine
Proceedings of the 38th annual Design Automation Conference
ATPG tools for delay faults at the functional level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The coupling model for function and delay faults
Journal of Electronic Testing: Theory and Applications
Robust Coupling Delay Test Sets
Journal of Electronic Testing: Theory and Applications
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Abstract: We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the circuit-under-test, necessary for employing existing gate-level delay fault test generators, is not available. It is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. It can also potentially be employed to supplement conventional test generators for gate-level circuits to reduce the cost of branch and bound strategies. A parameter called /spl Delta/ is used to control the number of functional faults targeted and thus the number of tests generated. If /spl Delta/ is unlimited, the functional test set detects every robustly testable path delay fault in any gate-level implementation of the given function. An appropriate subset of tests can be selected once the implementation is known. The test sets generated for various values of /spl Delta/ are fault simulated on gate-level realizations to demonstrate their effectiveness.