On testing delay faults in macro-based combinational circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Functional test generation for delay faults in combinational circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Universal delay test sets for logic networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
High-level function and delay testing for digital circuits
High-level function and delay testing for digital circuits
On effective criterion of path selection for delay testing
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
The coupling model for function and delay faults
Journal of Electronic Testing: Theory and Applications
On Performance Testing with Path Delay Patterns
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Complete Test Sets for Logic Functions
IEEE Transactions on Computers
Universal Test Sets for Logic Networks
IEEE Transactions on Computers
Realization-independent ATPG for designs with unimplemented blocks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level delay test generation for modular circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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One of the most challenging problems in high-level testing is to reduce the size of a high-level test set while ensuring an adequate fault coverage for various implementations of a function under test. A small and high-coverage test set called a robust coupling delay test set (RCDTS) is derived from the coupling delay test set proposed previously. A partial ordering relationship among delay tests in certain implementations called "restricted" gate networks is used to reduce the size of test sets. The RCDTS still detects all robust path delay faults. This result is extended further to the more general balanced inversion parity networks. A test generation program RTGEN for RCDTSs is then developed, and experiments with it show that significant test set reduction can be achieved.