Test-set preserving logic transformations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On testing delay faults in macro-based combinational circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Functional test generation for delay faults in combinational circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Scalable Test Generators for High-Speed Datapath Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Journal of Electronic Testing: Theory and Applications
Universal delay test sets for logic networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays
IEEE Transactions on Computers
Proceedings of the 38th annual Design Automation Conference
1.1 Test methodology for embedded cores which protects intellectual property
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Delay Fault Testing of Designs with Embedded IP Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
High-level function and delay testing for digital circuits
High-level function and delay testing for digital circuits
Realization-independent ATPG for designs with unimplemented blocks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Coupling Delay Test Sets
Journal of Electronic Testing: Theory and Applications
Hi-index | 0.00 |
We propose a high-level fault model, the coupling fault (CF) model, that aims to cover both functional and timing faults in an integrated way. The basic properties of CFs and the corresponding tests are analyzed, focusing on their relationship with other fault models and their test requirements. A test generation program COTEGE for CFs is presented. Experiments with COTEGE are described which show that (reduced) coupling test sets can efficiently cover standard stuck-at-0/1 faults in a variety of different realizations. The corresponding coupling delay tests detect all robust path delay faults in any realization of a logic function.