Hierarchical test generation under intensive global functional constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Hierarchical Test Program Development for Scan Testable Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Macro Testability: The Results of Production Device Applications
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Microprocessor based testing for core-based system on chip
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Delay fault testing of IP-based designs via symbolic path modeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Structural Fault Testing of Embedded Cores Using Pipelining
Journal of Electronic Testing: Theory and Applications
A novel test methodology for core-based system LSIs and a testing time minimization problem
ITC '98 Proceedings of the 1998 IEEE International Test Conference
High-coverage ATPG for datapath circuits with unimplemented blocks
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Delay Fault Testing of Designs with Embedded IP Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Test Requirements for Embedded Core-based Systems and IEEE P1500
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Delay Fault Testing of IP-Based Designs Via Symbolic Path Modeling
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Partial Core Encryption for Performance-Efficient Test of SOCs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
The coupling model for function and delay faults
Journal of Electronic Testing: Theory and Applications
Microprocessor based self schedule and parallel BIST for system-on-a-chip
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
| Hi-index | 0.00 |
Testing of embedded cores poses a great challenge. These cores cannot be tested in isolation because core I/Os are not directly accessible from ASIC I/Os. A novel test methodology is developed which generates a partial netlist for protection of intellectual property (IP) by performing structural analysis. This partial netlist is used in ASIC level test generation. For the remaining gates of the core, patterns are supplied to test those gates, which can be applied through only core scan chain. Another scheme is developed to select a few I/Os optimally to add boundary scan circuits to improve IP protection.