Using Partial Isolation Rings to Test Core-Based Designs
IEEE Design & Test
A Unifying Methodology for Intellectual Property and Custom Logic Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
1.1 Test methodology for embedded cores which protects intellectual property
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A low overhead design for testability and test generation technique for core-based systems-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CLIP: circuit level IC protection through direct injection of process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The isolation of a core through full I/O scan helps ease SOC test challenges;yet the performance of high-speed SOCs is significantly hampered.We propose a partial core encryption methodology wherein thecore vendor unveils only a small part of the core logic, successfully satisfyingcore IP protection requirements. Once the partially encryptedcores are merged into an SOC, the system integrator performs test generationon the visible SOC logic only, greatly reducing the test generationeffort expended. By utilizing the test data provided by the core vendoras well, the SOC integrator can test the SOC with no performancedegradation. We present an efficient fault analysis based core encryptionalgorithm which is guided by judiciously computed testability measures.The experimental results confirm the significantly high encryption levelsattained by the proposed encryption algorithm.