Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates
Proceedings of the IEEE International Test Conference on Test and Design Validity
Test Pattern Generation with Restrictors
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Efficient Test-Response Compression for Multiple-Output Cicuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
A framework for testing core-based systems-on-a-chip
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Test Bus Sizing for System-on-a-Chip
IEEE Transactions on Computers
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
Modular logic built-in self-test for IP cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A novel test methodology for core-based system LSIs and a testing time minimization problem
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Hierarchical Infrastructure for SoC Test Management
IEEE Design & Test
IEEE Transactions on Computers
Partial Core Encryption for Performance-Efficient Test of SOCs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
2.5D system integration: a design driven system implementation schema
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A P1500-Compatible Programmable BIST Aapproach for the Test of Embedded Flash Memories
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A non-intrusive isolation approach for soft cores
Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Test-access mechanism optimization for core-based three-dimensional SOCs
Microelectronics Journal
2.5-Dimensional VLSI system integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Core-based designs pose a significant test challenge. A simple and fast solution is to place a full isolation ring (i.e., boundary scan) around each core, however, the area and performance overhead for this may not be acceptable in many applications. A systematic method is presented for designing a partial isolation ring that provides the same fault coverage as a full isolation ring, but avoids adding MUXes on critical timing paths and reduces area overhead. Efficient ATPG techniques are used to analyze the user-defined logic surrounding the core and identify a maximal set of core inputs and outputs that do not need to be included in the partial isolation ring. In the case where one core is driving another core, the procedure identifies a maximal set of isolation ring elements that can be removed from the interface between the cores. Several different partial isolation ring selection strategies that vary in computational complexity are described. Experimental results are shown comparing the different strategies.