Implementing Macro Test in Silicon Compiler Design
IEEE Design & Test
Using Partial Isolation Rings to Test Core-Based Designs
IEEE Design & Test
An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores
Proceedings of the IEEE International Test Conference
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
Proceedings of the IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
1.2 Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
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HD2BIST a complete hierarchical framework for BIST scheduling, data-patterns delivery, and diagnosis of complex systems maximizes and simplifies the reuse of built-in test architectures. HD2BIST optimizes flexibility for chip designers planning an overall SoC test strategy by defining a test access method that provides direct virtual access to each core of the system.