Implementing Macro Test in Silicon Compiler Design
IEEE Design & Test
HIST: A Methodology for the Automatic Insertion of a Hierarchical Self Test
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores
Proceedings of the IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
HD-BIST: A Hierarchical Framework for BIST Scheduling and Diagnosis in SoCs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Benefits of a SoC-Specific Test Methodology
IEEE Design & Test
A Programmable BIST Architecture for Clusters of Multiple-Port SRAMs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A Hierarchical Infrastructure for SoC Test Management
IEEE Design & Test
Searching for Global Test Costs Optimization in Core-Based Systems
Journal of Electronic Testing: Theory and Applications
A New FPGA for DSP Applications Integrating BIST Capabilities
Journal of Electronic Testing: Theory and Applications
Agent-based test and repair of distributed systems
Journal of Embedded Computing - Low-power Embedded Systems
An novel methodology for reducing SoC test data volume on FPGA-based testers
Proceedings of the conference on Design, automation and test in Europe
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This paper proposes HD2BIST, a complete hierarchicalframework for BIST scheduling, data patterns delivering,and diagnosis of a complex system including embeddedcoreswith different test requirements as Full Scan cores,Partial Scan cores, or BIST-ready cores. The main goal ofHD2BIST is to maximize and simplify the reuse of thebuilt-in test architectures, giving the chip designer thehighest flexibility in planning the overall SoC teststrategy. HD2BIST defines a Test Access Method (TAM)able to provide a direct "virtual" access to each core ofthe system, and can be conceptually considered as apowerful complement to the P1500 standard, whose maintarget is to make the test interface of each coreindependent from the vendor.