A Programmable BIST Architecture for Clusters of Multiple-Port SRAMs

Authors:
Alfredo BENSO;Stefano DI CARLO;Giorgio DI NATALE;Paolo PRINETTO
Affiliations:
-;-;-;-
Venue:
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Year:
2000

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Abstract

This paper presents a BIST architecture, based on asingle micro-programmable BIST Processor and a set ofmemory Wrappers, designed to simplify the test of asystem containing many distributed multi-port SRAMs ofdifferent sizes (number of bits, number of words), accessprotocol (asynchronous, synchronous), and timing.