ACM Computing Surveys (CSUR)
Diagnosis and Repair of Memory with Coupling Faults
IEEE Transactions on Computers
Embedded DRAM technology opportunities and challenges
IEEE Spectrum
Diagnostic testing of embedded memories using BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Memory fault diagnosis by syndrome compression
Proceedings of the conference on Design, automation and test in Europe
Error catch and analysis for semiconductor memories using march tests
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Using March Tests to Test SRAMs
IEEE Design & Test
RAMSES: A Fast Memory Fault Simulator
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
March-based RAM diagnosis algorithms for stuck-at and coupling faults
Proceedings of the IEEE International Test Conference 2001
A built-in self-test and self-diagnosis scheme for embedded SRAM
ATS '00 Proceedings of the 9th Asian Test Symposium
A Programmable BIST Architecture for Clusters of Multiple-Port SRAMs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Hardware Compression Speeds on Bitmap Fail Display
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Integrated Diagnostics for Embedded Memory Built-in Self Test on PowerPCTM Devices
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
Enabling Embedded Memory Diagnosis via Test Response Compression
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
The Testability Features of the 3rd Generation Coldfire® Family of Microprocessors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testing content-addressable memories using functional fault models and march-like algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An accumulator-based compaction scheme for online BIST of RAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fault models for embedded-DRAM macros
Proceedings of the 46th Annual Design Automation Conference
Testing methodology of embedded DRAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A system-on-chip (SOC) usually consists of many memory cores with different sizes and functionality, and they typically represent a significant portion of the SOC and therefore dominate its yield. Diagnostics for yield enhancement of the memory cores thus is a very important issue. In this paper we present two data compression techniques that can be used to speed up the transmission of diagnostic data from the embedded RAM built-in self-test (BIST) circuit that has diagnostic support to the external tester. The proposed syndrome-accumulation approach compresses the faulty-cell address and March syndrome to about 28% of the original size on average under the March-17N diagnostic test algorithm. The key component of the compressor is a novel syndrome-accumulation circuit, which can be realized by a content-addressable memory. Experimental results show that the area overhead is about 0.9% for a 1Mb SRAM with 164 faults. A tree-based compression technique for word-oriented memories is also presented. By using a simplified Huffman coding scheme and partitioning each 256-bit Hamming syndrome into fixed-size symbols, the average compression ratio (size of original data to that of compressed data) is about 10, assuming 16-bit symbols. Also, the additional hardware to implement the tree-based compressor is very small. The proposed compression techniques effectively reduce the memory diagnosis time as well as the tester storage requirement.