Memory fault diagnosis by syndrome compression
Proceedings of the conference on Design, automation and test in Europe
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test
Journal of Electronic Testing: Theory and Applications
March-Based RAM Diagnosis Algorithms for Stuck-At and Coupling Faults
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Hardware/Software Co-testing of Embedded Memories in Complex SOCs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A System-layer Infrastructure for SoC Diagnosis
Journal of Electronic Testing: Theory and Applications
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Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in self-test (BIST), is rapidly becoming the most acceptable solution. We propose a BISD design and a fault diagnosis system for embedded SRAM. It supports manufacturing test as well as diagnosis for design verification and yield improvement. The proposed BISD circuit is on-line programmable for its March test algorithms. Test chips have been designed and implemented. Our experimental results show that the BISD hardware overhead is about 2.4% for a typical 128 Kb SRAM and only 0.65% for a 2 Mb SRAM.