Test Scheduling and Control for VLSI Built-in Self-Test
IEEE Transactions on Computers
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Processor-programmable memory BIST for bus-connected embedded memories
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
An on-chip march pattern generator for testing embedded memory cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A built-in self-test and self-diagnosis scheme for embedded SRAM
ATS '00 Proceedings of the 9th Asian Test Symposium
Test Scheduling of BISTed Memory Cores for SOC
ATS '02 Proceedings of the 11th Asian Test Symposium
An Effective Distributed BIST Architecture for RAMs
ETW '00 Proceedings of the IEEE European Test Workshop
A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis
ATS '01 Proceedings of the 10th Asian Test Symposium
A P1500 Compliant Programable BistShell for Embedded Memories
MTDT '01 Proceedings of the International Workshop on Memory Technology, Design, and Testing (MTDT'01)
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Testing a System-On-a-Chip with Embedded Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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A novel approach for testing embedded memories in complexsystems-on-a-chip (SOCs) is presented. The proposedsolution aims to balance the usage of the existing on-chipresources and dedicated design for test (DFT) hardwaresuch that the functional power constraints are not exceededduring test while trading-off the testing time againstDFT area and performance overhead. The suitability ofsoftware-centric and hardware-centric approaches for embeddedmemory testing is examined and to combine the advantagesof both directions, a new built-in self-test (BIST)-basedmethod, called hardware/software co-testing, is introduced.The proposed solution is programmable, scalableand guarantees low routing overhead.