Discrete and Combinatoral Mathematics: An Applied Introduction 2nd Ed.
Discrete and Combinatoral Mathematics: An Applied Introduction 2nd Ed.
Computer Networks
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
A scheme for overlaying concurrent testing of VLSI circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Graph partitioning for concurrent test scheduling in VLSI circuit
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Test Scheduling in High Performance VLSI System Implementations
IEEE Transactions on Computers
Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems
Journal of Electronic Testing: Theory and Applications
Allocation Techniques for Reducing BIST Area Overhead ofData Paths
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
An IEEE 1149.1 Compliant Test Control Architecture
Journal of Electronic Testing: Theory and Applications
Efficient BIST hardware insertion with low test application time for synthesized data paths
DATE '99 Proceedings of the conference on Design, automation and test in Europe
An Integrated Framework for the Design and Optimization of SOC Test Solutions
Journal of Electronic Testing: Theory and Applications
Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Comparison of Classical Scheduling Approaches in Power-Constrained Block-Test Scheduling
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Using BIST Control for Pattern Generation
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Power-Conscious Test Synthesis and Scheduling
IEEE Design & Test
Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment
EURO-DAC '91 Proceedings of the conference on European design automation
Test scheduling and controller synthesis in the CADDY-system
EURO-DAC '91 Proceedings of the conference on European design automation
A Graph-Based Approach to Power-Constrained SOC Test Scheduling
Journal of Electronic Testing: Theory and Applications
Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints
Journal of Electronic Testing: Theory and Applications
Testability Trade-Offs for BIST Data Paths
Journal of Electronic Testing: Theory and Applications
Hardware/Software Co-testing of Embedded Memories in Complex SOCs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Concurrent BIST synthesis and test scheduling using genetic algorithms
International Journal of Computers and Applications
Configuring flip-flops to BIST registers
ITC'94 Proceedings of the 1994 international conference on Test
Test scheduling for high performance VLSI system implementations
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
| Hi-index | 14.98 |
The test scheduling problem for equal length and unequal length tests for VLSI circuits using built-in self-test (BIST) has been modeled. A hierarchical model for VLSI circuit testing is introduced. The test resource sharing model from C. Kime and K. Saluja (1982) is employed to exploit the potential parallelism. Based on this model, very efficient suboptimum algorithms are proposed for defining test schedules for both the equal length test and unequal length test cases. For the unequal length test case, three different scheduling disciplines are defined, and scheduling algorithms are given for two of the three cases. Data on algorithm performance are presented. The issue of the control of the test schedule is also addressed, and a number of structures are proposed for implementation of control.