Test Schedules for VLSI Circuits Having Built-In Test Hardware
IEEE Transactions on Computers - The MIT Press scientific computation series
Test Scheduling and Control for VLSI Built-in Self-Test
IEEE Transactions on Computers
A Testability Strategy for Microprocessor Architecture
IEEE Design & Test
Open-ended system for high-level synthesis of flexible signal processors
EURO-DAC '90 Proceedings of the conference on European design automation
Experience in functional-level test generation and fault coverage in a silicon compiler
EURO-DAC '90 Proceedings of the conference on European design automation
SYNTEST: an environment for system-level design for test
EURO-DAC '92 Proceedings of the conference on European design automation
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The CAD implementation of a testability strategy for chips as designed with the Cathedral-II/2nd silicon compilation environment is presented. Emphasis will be on the software tools accomplishing the test assembly. These tools are fully integrated with synthesis, place and route and module generation programs. The hierarchy present in the design has been exploited to assemble the test patterns in an hierarchical way. Our approach allows to arrive at a fully testable chip, with a very high fault coverage.