An artificial intelligence approach to test generation
An artificial intelligence approach to test generation
State assignment using a new embedding method based on an intersecting cube theory
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment
EURO-DAC '91 Proceedings of the conference on European design automation
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During the design cycle of VLSI circuits, test vector generation is often a very time consuming and costly step.Many strategies concerning automatic test pattern generation have been published. Usually they are restrictive and consider the circuit as an undifferentiated mass of gates while ignoring the hierarchy used during the design process. The test vectors so generated are based on the traditional stuck-at-fault model.In this paper, an ATPG methodology is presented which is based on "functional testing" of each block logic and not on testing each gate or net. The methodology is not limited to combinatorial logic or scan-path designs, and here, is applied to datapath circuits composed of functional blocks (such as ALU, etc) and to state machines.