A kernel-finding state assignment algorithm for multi-level logic
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An implementation of a state assignment heuristic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A State Variable Assignment Method for Asynchronous Sequential Switching Circuits
Journal of the ACM (JACM)
Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics)
A Row Assignment for Delay-Free Realizations of Flow Tables Without Essential Hazards
IEEE Transactions on Computers
Optimized Synthesis of Concurrently Checked Controllers
IEEE Transactions on Computers
FSM decomposition revisited: Algebraic structure theory applied to MCNC benchmark FSMs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Efficient constrained encoding for VLSI sequential logic synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
State assignment for hardwired VLSI control units
ACM Computing Surveys (CSUR)
Optimized state assignment of single fault tolerant FSMs based on SEC codes
DAC '93 Proceedings of the 30th international Design Automation Conference
A fast and robust exact algorithm for face embedding
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Experience in functional-level test generation and fault coverage in a silicon compiler
EURO-DAC '90 Proceedings of the conference on European design automation
State assignment of controllers for optimal area implementation
EURO-DAC '90 Proceedings of the conference on European design automation
Optimization of micro-controllers by partitioning
EURO-DAC '91 Proceedings of the conference on European design automation
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The controller state assignment methodology proposed here features two improvements over existing methods. First, a larger set of predictive minimizations in the control flowgraph is performed. Secondly, the embedding phase uses a new theory of intersecting cubes in the Boolean lattice. Practical results using the VLSI Technology Logic-Synthesizer on both PLA and multi-level logic demonstrate the effectiveness of the approach.