State assignment using a new embedding method based on an intersecting cube theory
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
NOVA: state assignment of finite state machines for optimal two-level logic implementations
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics)
State assignment for hardwired VLSI control units
ACM Computing Surveys (CSUR)
Optimized state assignment of single fault tolerant FSMs based on SEC codes
DAC '93 Proceedings of the 30th international Design Automation Conference
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The state assignment of controllers presented here aims at preparing further minimizations of the next-state and output logic implementation on standard cells. This is done by detecting situations in the control flowgraph leading to these further minimizations, deducing constraints on the state assignment and finding a solution on the hypercube satisfying them. The originality of this paper is to propose situations minimizing both the gate area and the wiring area. For this purpose, full collapsing product term constraints are defined and are respected first. In a second step, constraints leading to factorizations are respected as long as they do not prevent the previous factorizations. Results on global area decrease are given on controller benchmarks.