Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Computer-aided synthesis of pla-based systems
Computer-aided synthesis of pla-based systems
A unified approach to the decomposition and re-decomposition of sequential machines
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Initializability Consideration in Sequential Machine Synthesis
IEEE Transactions on Computers
Finite state machine synthesis with fault tolerant test function
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
State assignment using input/output functions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Communication based logic partitioning
EURO-DAC '92 Proceedings of the conference on European design automation
State assignment for hardwired VLSI control units
ACM Computing Surveys (CSUR)
Optimized state assignment of single fault tolerant FSMs based on SEC codes
DAC '93 Proceedings of the 30th international Design Automation Conference
An efficient procedure for the synthesis of fast self-testable controller structures
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Hardware-software-codesign of application specific microcontrollers with the ASM environment
EURO-DAC '94 Proceedings of the conference on European design automation
Incremental re-encoding for symbolic traversal of product machines
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Automatic synthesis of a dual-PLA controller with a counter
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
An algorithm for improving partitions of pin-limited multi-chip systems
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Formal Methods in System Design
Algorithms for the optimal state assignment of asynchronous state machines
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
State assignment of controllers for optimal area implementation
EURO-DAC '90 Proceedings of the conference on European design automation
Fast heuristic algorithms for finite state machine minimization
EURO-DAC '91 Proceedings of the conference on European design automation
MACHETE: synthesis of sequential machines for easy testability
EURO-DAC '91 Proceedings of the conference on European design automation
Optimization of micro-controllers by partitioning
EURO-DAC '91 Proceedings of the conference on European design automation
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
| Hi-index | 0.00 |
The problem of encoding the states of a synchronous Finite State Machine (FSM), so that the area of a two-level implementation of the combinational logic is minimized, is addressed. As in previous approaches, the problem is reduced to the solution of the combinatorial optimization problems defined by the translation of the cover obtained by a multiple-valued logic minimization or by a symbolic minimization into a compatible Boolean representation. In this paper we present algorithms for their solution, based on a new theoretical framework that offers advantages over previous approaches to develop effective heuristics. The algorithms are part of NOVA, a program for optimal encoding of control logic. Final areas averaging 20% less than other state assignment programs and 30% less than the best random solutions have been obtained. Literal counts averaging 30% less than the best random solutions have been obtained.