Flex: A High-Level Language for Specifying Customized Microprocessors
IEEE Transactions on Software Engineering
General decomposition of sequential machines: relationships to state assignment
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
State assignment using a new embedding method based on an intersecting cube theory
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
NOVA: state assignment of finite state machines for optimal two-level logic implementations
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Horizontal partitioning of PLA-based finite state machines
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
High-level synthesis: current status and future directions
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Automated synthesis of data paths in digital systems (design space)
Automated synthesis of data paths in digital systems (design space)
Flexible controlpath microarchitecture synthesis based on artificial intelligence
EURO-DAC '92 Proceedings of the conference on European design automation
Architectural partitioning of control memory for application specific programmable processors
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
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In this paper, we present a new partitioning method for Finite State Machines (FSMs). The method is particularly well suited for μ-controller circuits. It consists in grouping the μ-instructions of the control graph into classes according to a compatibility property of the output values. Only one sequence of output values is then generated for all μ-instructions of a given class. The resulting structure is composed of three machines: a STATE machine which generates the next states, a COMMAND machine and a FILTER machine. The COMMAND outputs and the FILTER outputs are merged via a logical AND to obtain the final outputs. This structure leads to an area reduction of 34 % to 65 % for the examples presented.