Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
The mimola design system: Tools for the design of digital processors
DAC '84 Proceedings of the 21st Design Automation Conference
High-level synthesis: technology transfer to industry
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Data path allocation using an extended binding model
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Sequencer-based data path synthesis of regular iterative algorithms
DAC '94 Proceedings of the 31st annual Design Automation Conference
A new technique for exploiting regularity in data path synthesis
EURO-DAC '94 Proceedings of the conference on European design automation
Optimization of micro-controllers by partitioning
EURO-DAC '91 Proceedings of the conference on European design automation
Improved force-directed scheduling
EURO-DAC '91 Proceedings of the conference on European design automation
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The third High-Level Synthesis Workshop was held in January of this year at Orcas Island, Washington*. What distinguished this workshop from its predecessors was that participants were asked to submit papers describing the application of their systems and algorithms to a set of benchmarks. This proved to be a successful method for comparing the extensive research being conducted in this area of CAD. In this paper, we will briefly describe the benchmarks and use them as a foundation for outlining the major themes in the research work presented at the workshop. The paper concludes with a summary of the discussions held during the course of the workshop on the future development of the high-level synthesis benchmark suite.