Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Importance Sampling for Ising Computers Using One-Dimensional Cellular Automata
IEEE Transactions on Computers
Scheduling and binding algorithms for high-level synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A Decomposition Approach for Balancing Large-Scale Acyclic Data Flow Graphs
IEEE Transactions on Computers
Optimum and heuristic data path scheduling under resource constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The combination of scheduling, allocation, and mapping in a single algorithm
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Automated micro-roll-back self-recovery synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Fast and near optimal scheduling in automatic data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Scheduling for functional pipelining and loop winding
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Redundant operator creation: a scheduling optimization technique
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
System clock estimation based on clock slack minimization
EURO-DAC '92 Proceedings of the conference on European design automation
Performance-driven interconnection optimization for microarchitecture synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
A neural network based algorithm for the scheduling problem in high-level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Generating pipelined datapaths using reduction techniques to shorten critical paths
EURO-DAC '92 Proceedings of the conference on European design automation
A layout estimation algorithm for RTL datapaths
DAC '93 Proceedings of the 30th international Design Automation Conference
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
Rotation scheduling: a loop pipelining algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
Microarchitectural synthesis of VLSI designs with high test concurrency
DAC '94 Proceedings of the 31st annual Design Automation Conference
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
EURO-DAC '94 Proceedings of the conference on European design automation
A multiple clocking scheme for low power RTL design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
An optimal clock period selection method based on slack minimization criteria
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Rapid performance estimation for system design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Retargetable assembly code generation by bootstrapping
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Fast Implementation of 3-D Digital Filters Via SystolicArray Processors
Multidimensional Systems and Signal Processing
A new optimization technique for improving resource exploitation and critical path minization
ISSS '97 Proceedings of the 10th international symposium on System synthesis
A test synthesis approach to reducing BALLAST DFT overhead
DAC '97 Proceedings of the 34th annual Design Automation Conference
A scheme for integrated controller-datapath fault testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
VLSI design synthesis with testability
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
High-level synthesis: current status and future directions
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An effective methodology for functional pipelining
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A scheduling method by stepwise expansion in high-level synthesis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Efficiency improvements for force-directed scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Accurate layout area and delay modeling for system level design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Estimation of BIST Resources During High-Level Synthesis
Journal of Electronic Testing: Theory and Applications
Lower and upper bounds on the switching activity in scheduled data flow graphs
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
An Ada design for the windowing, tasking, and processing of multi-dimensional large arrays
WADAS '89 Proceedings of the sixth Washington Ada symposium on Ada
An Efficient Algorithm for the Computation of the MultidimensionalDiscrete Fourier Transform
Multidimensional Systems and Signal Processing
A bypass scheme for core-based system fault testing
Proceedings of the conference on Design, automation and test in Europe
Integrated test of interacting controllers and datapaths
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 14th international symposium on Systems synthesis
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
A Fast Algorithm for Matrix Multiplication and Its Efficient Realization on Systolic Arrays
Cybernetics and Systems Analysis
Structural Fault Testing of Embedded Cores Using Pipelining
Journal of Electronic Testing: Theory and Applications
Algorithms for High-Level Synthesis
IEEE Design & Test
Fast Combinatorial RNS Processors for DSP Applications
IEEE Transactions on Computers
Bit-modular defect/fault-tolerant convolvers
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Design Space Exploration for Data Path Synthesis
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
1.3 Parallelism in Structural Fault Testing of Embedded Cores
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Predicting the generation and the consumption of an open system
Systems Analysis Modelling Simulation
A neural net based self organising scheduling algorithm
EURO-DAC '90 Proceedings of the conference on European design automation
Towards a global solution to high level synthesis problems
EURO-DAC '90 Proceedings of the conference on European design automation
Improved force-directed scheduling
EURO-DAC '91 Proceedings of the conference on European design automation
Combining Extended Retiming and Unfolding for Rate-Optimal Graph Transformation
Journal of VLSI Signal Processing Systems
An Efficient Parallel Algorithm to Solve Block-Toeplitz Systems
The Journal of Supercomputing
Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages
IEEE Transactions on Computers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Combining extended retiming and unfolding for rate-optimal graph transformation
Journal of VLSI Signal Processing Systems
Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Block Data Processing Using Commercial Processors
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Time-constrained loop scheduling with minimal resources
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
ILP optimal scheduling for multi-module memory
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Power optimization with power islands synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast hybrid matrix multiplication algorithms
Cybernetics and Systems Analysis
Feedback-Based global instruction scheduling for GPGPU applications
ICCSA'12 Proceedings of the 12th international conference on Computational Science and Its Applications - Volume Part I
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