PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A global resource-constrained parallelization technique
ICS '89 Proceedings of the 3rd international conference on Supercomputing
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
Perfect Pipelining: A New Loop Parallelization Technique
ESOP '88 Proceedings of the 2nd European Symposium on Programming
Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
ALPS: an algorithm for pipeline data path synthesis
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Scheduling for functional pipelining and loop winding
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Incremental tree height reduction for high level synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Redundant operator creation: a scheduling optimization technique
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis from VHDL with exact timing constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Superpipelined control and data path synthesis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Harmonic scheduling of linear recurrences for digital filter design
EURO-DAC '92 Proceedings of the conference on European design automation
High-level synthesis of scalable architectures for IIR filters using multichip modules
DAC '93 Proceedings of the 30th international Design Automation Conference
Rotation scheduling: a loop pipelining algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
Integrating program transformations in the memory-based synthesis of image and video algorithms
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Minimization of memory traffic in high-level synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Global scheduling for high-level synthesis applications
DAC '94 Proceedings of the 31st annual Design Automation Conference
Generating several solutions for the scheduling problem in high-level synthesis
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Semi-dynamic scheduling of synchronization-mechanisms
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Achieving Full Parallelism Using Multidimensional Retiming
IEEE Transactions on Parallel and Distributed Systems
High throughput pipelined data path synthesis by conserving the regularity of nested loops
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Resource contrained modulo scheduling with global resource sharing
Proceedings of the 11th international symposium on System synthesis
An effective methodology for functional pipelining
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Time constrained modulo scheduling with global resource sharing
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A code-motion pruning technique for global scheduling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware-software cosynthesis for microcontrollers
Readings in hardware/software co-design
Efficient scheduling of conditional behaviors for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Transient power management through high level synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
High-level synthesis of distributed logic-memory architectures
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Combining MBP-speculative computation and loop pipelining in high-level synthesis
EDTC '95 Proceedings of the 1995 European conference on Design and Test
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Area and performance optimizations in path-based scheduling
EURO-DAC '91 Proceedings of the conference on European design automation
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A scheduling algorithm for optimization and early planning in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Multi-token resource sharing for pipelined asynchronous systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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A new approach called Percolation Based Synthesis for the scheduling phase of High Level Synthesis (HLS) is presented. We discuss some new techniques (which are implemented in our tools) for compaction of flow graphs beyond basic blocks limits, which can produce order of magnitude speed ups versus serial execution. Our algorithm applies to programs with conditional jumps, loops and multicycle pipelined operations. In order to schedule under resource constraints we start by first finding the optimal schedule (without constraints) and then add heuristics to map the optimal schedule onto the given system. We argue that starting from an optimal schedule is one of the most important factors in scheduling because it offers the user flexibility to tune the heuristics and gives him a good bound for the resource constrained schedule. This scheduling algorithm is integrated with synthesis tool which uses VHDL as input description and produces a structural netlist of generic register-transfer components and a unit based control table as output. We show that our algorithm obtains better results than previously published algorithms.