Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Synthesis using path-based scheduling: algorithms and exercises
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Splicer: a heuristic approach to connectivity binding
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Graph Algorithms
Interconnect optimisation during data path allocation
EURO-DAC '90 Proceedings of the conference on European design automation
Data-path synthesis using path analysis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A code-motion pruning technique for global scheduling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Combining MBP-speculative computation and loop pipelining in high-level synthesis
EDTC '95 Proceedings of the 1995 European conference on Design and Test
PPS: a pipeline path-based scheduler
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A Constructive Method for Exploiting Code Motion
ISSS '96 Proceedings of the 9th international symposium on System synthesis
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This paper describes the area and performance optimizations implemented in the As-Fast-As-Possible (AFAP) scheduling algorithm. The AFAP scheduling algorithm is a path-based technique that finds the minimum number of control steps for all possible sequences of operations in the control-flow graph, under given constraints. Area requirements for functional units, such as their number and type, are translated into constraints which are then met exactly. The number of registers is also minimized. The performance optimizations included in this paper are concerned mainly with the scheduling of loops.