Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Synthesis using path-based scheduling: algorithms and exercises
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Performance analysis and optimization of schedules for conditional and loop-intensive specifications
DAC '94 Proceedings of the 31st annual Design Automation Conference
Compiling pascal programs into silicon (design automation, hardware synthesis)
Compiling pascal programs into silicon (design automation, hardware synthesis)
Area and performance optimizations in path-based scheduling
EURO-DAC '91 Proceedings of the conference on European design automation
Formulation and evaluation of scheduling techniques for control flow graphs
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
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This paper presents a scheduling algorithm that improves on other approaches when dealing with the synthesis of control-flow dominated behavioral descriptions. It achieves this through the use of a constraint-driven path-based scheduling algorithm. The suboptimality of the original path-based algorithms when dealing with loops is overcome through a new technique for pipelining different loop iterations during execution path generation. Results show that the algorithm always generates the fastest solution in terms of clock cycles.