Implementation optimization techniques for architecture synthesis of application-specific processors
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Data-path synthesis using path analysis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A tree-based scheduling algorithm for control-dominated circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Incorporating speculative execution in exact control-dependent scheduling
DAC '94 Proceedings of the 31st annual Design Automation Conference
Performance analysis and optimization of schedules for conditional and loop-intensive specifications
DAC '94 Proceedings of the 31st annual Design Automation Conference
High-level synthesis in an industrial environment
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Generating several solutions for the scheduling problem in high-level synthesis
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Resource contrained modulo scheduling with global resource sharing
Proceedings of the 11th international symposium on System synthesis
Time constrained modulo scheduling with global resource sharing
DATE '99 Proceedings of the conference on Design, automation and test in Europe
PPS: a pipeline path-based scheduler
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Symbolic Binding for Clustered VLIW ASIPs
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Area and performance optimizations in path-based scheduling
EURO-DAC '91 Proceedings of the conference on European design automation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Path-based scheduling algorithms consider all possible sequences of operations (called paths) in a control-flow graph. Unlike most scheduling techniques used in high-level synthesis, they stress optimization across conditional branches. This paper presents several path-based algorithms. An exact algorithm finds the minimum number of control steps required for each possible path being executed. Heuristic solutions were also implemented. Extensive application of these algorithms to the benchmarks of the High-Level Synthesis Workshop showed the practical feasibility of such methods.