Optimal scheduling and allocation of embedded VLSI chips
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Synthesis using path-based scheduling: algorithms and exercises
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
EURO-DAC '94 Proceedings of the conference on European design automation
Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator
DAC '98 Proceedings of the 35th annual Design Automation Conference
A bandwidth-efficient architecture for media processing
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Lower bound on latency for VLIW ASIP datapaths
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Retargetable Compilers for Embedded Core Processors: Methods and Experience in Industrial Applications
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Code Generation for Embedded Processors
Code Generation for Embedded Processors
Design Challenges for New Application-Specific Processors
IEEE Design & Test
Some Experiments in Local Microcode Compaction for Horizontal Machines
IEEE Transactions on Computers
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The paper proposes a symbolic framework to address the binding problem for embedded VLIW ASIPs. Alternative objective functions as well as trade-offs relevant to the binding phase of code generation for embedded processors are presented and discussed. Experimental results obtained for a number of benchmarks extracted from the literature empirically demonstrate the promise of our approach.