Integer and combinatorial optimization
Integer and combinatorial optimization
Relative scheduling under timing constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Optimal VLSI architectural synthesis: area, performance and testability
Optimal VLSI architectural synthesis: area, performance and testability
Incorporating speculative execution in exact control-dependent scheduling
DAC '94 Proceedings of the 31st annual Design Automation Conference
How datapath allocation affects controller delay
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Resource contrained modulo scheduling with global resource sharing
Proceedings of the 11th international symposium on System synthesis
Time constrained modulo scheduling with global resource sharing
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Optimal acyclic fine-grain scheduling with cache effects for embedded and real time systems
Proceedings of the ninth international symposium on Hardware/software codesign
Protocol selection and interface generation for HW-SW codesign
Readings in hardware/software co-design
Introduction to the Scheduling Problem
IEEE Design & Test
Optimal Clock Period for Synthesized Data Paths
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Symbolic Binding for Clustered VLIW ASIPs
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
| Hi-index | 0.00 |