Knowledge based control in micro-architecture design
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
HERCULES—a system for high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An Artificial Intelligence Approach to VLSI Design
An Artificial Intelligence Approach to VLSI Design
An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal scheduling and allocation of embedded VLSI chips
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Control optimization based on resynchronization of operations
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis from VHDL with exact timing constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Flexible timing specification in a VHDL synthesis subset
EURO-DAC '92 Proceedings of the conference on European design automation
Subtype concept of VHDL for synthesis constraints
EURO-DAC '92 Proceedings of the conference on European design automation
Comparative design validation based on event pattern mappings
DAC '93 Proceedings of the 30th international Design Automation Conference
Timing preserving interface transformations for the synthesis of behavioral VHDL
EURO-DAC '94 Proceedings of the conference on European design automation
Software synthesis for real-time information processing systems
LCTES '95 Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Scheduling using behavioral templates
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Semi-dynamic scheduling of synchronization-mechanisms
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Real-time multi-tasking in software synthesis for information processing systems
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Specification and management of timing constraints in behavioral VHDL
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Specification of interface components for synchronous data paths
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
A methodology and algorithms for the design of hard real-time multitasking ASICs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Early evaluation techniques for low power binding
Proceedings of the 2002 international symposium on Low power electronics and design
Real-time multi-tasking in software synthesis for information processing systems
Readings in hardware/software co-design
IEEE Design & Test
Multi-thread graph: a system model for real-time embedded software synthesis
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An efficient and versatile scheduling algorithm based on SDC formulation
Proceedings of the 43rd annual Design Automation Conference
A low-power scheduling tool for system on a chip designs
WSEAS Transactions on Circuits and Systems
An Hybrid Soft Computing Approach for Automated Computer Design
Proceedings of the 2006 conference on STAIRS 2006: Proceedings of the Third Starting AI Researchers' Symposium
Exploiting area/delay tradeoffs in high-level synthesis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Scheduling techniques are used in high-level synthesis of integrated circuits. Traditional scheduling techniques assume fixed execution delays for the operations. For the synthesis of ASIC designs that interface with external signals and events, operations with unbounded delays, i.e. delays unknown at compile time, must also be considered. We present a relative scheduling technique that supports operations with fixed and unbounded delays. The technique satisfies the timing constraints imposed by the user, which places bounds between the activation of operations. We analyze a novel property called well-posedness of timing constraints that is used to identify consistency of constraints in the presence of unbounded delay operations, and present an approach to relative scheduling that yields a minimum schedule that satisfies the constraints, or detects if no schedule exists, in polynomial time.