VLSI design language standardization effort in Japan
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Relative scheduling under timing constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
VHDL as Input for High-Level Synthesis
IEEE Design & Test
High-level synthesis of digital circuits using global scheduling and binding algorithms
High-level synthesis of digital circuits using global scheduling and binding algorithms
EURO-DAC '94 Proceedings of the conference on European design automation
Timing constraint specification and synthesis in behavioral VHDL
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
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