High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Compiling VHDL into a high-level synthesis design representation
EURO-DAC '92 Proceedings of the conference on European design automation
Subtype concept of VHDL for synthesis constraints
EURO-DAC '92 Proceedings of the conference on European design automation
Synthesis of VHDL concurrent processes
EURO-DAC '94 Proceedings of the conference on European design automation
Timing preserving interface transformations for the synthesis of behavioral VHDL
EURO-DAC '94 Proceedings of the conference on European design automation
The Synthesis Approach to Digital System Design
The Synthesis Approach to Digital System Design
Specification and management of timing constraints in behavioral VHDL
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
| Hi-index | 0.00 |