Relative scheduling under timing constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-level synthesis from VHDL with exact timing constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
VHDL as Input for High-Level Synthesis
IEEE Design & Test
Device selection for system partitioning
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Timing constraint specification and synthesis in behavioral VHDL
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Resource sharing in hierarchical synthesis
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An approach for extracting RT timing information to annotate algorithmic VHDL specifications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Verification by simulation comparison using interface synthesi
Proceedings of the conference on Design, automation and test in Europe
Cross-level hierarchical high-level synthesis
Proceedings of the conference on Design, automation and test in Europe
PuMA++: From Behavioral Specification to Multi-FPGA-Prototype
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
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