High-level synthesis from VHDL with exact timing constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Timing preserving interface transformations for the synthesis of behavioral VHDL
EURO-DAC '94 Proceedings of the conference on European design automation
Behavioral synthesis methodology for HDL-based specification and validation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Simulation-Based Verification for High-Level Synthesis
IEEE Design & Test
Observable Time Windows: Verifying the Results of High-Level Synthesis
EDTC '96 Proceedings of the 1996 European conference on Design and Test
System synthesis using behavioural descriptions
EURO-DAC '90 Proceedings of the conference on European design automation
CASCH: a scheduling algorithm for "high level"-synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
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One of the main tasks within the high-level synthesis (HLS) process is the verification problem to prove automatically the correctness of the synthesis results. Currently, the results are usually checked by simulation. In consequence, both the behavioral specification and the HLS results have to be simulated by the same set of test vectors. Due to the HLS and the inherent changes in the cycle-by-cycle behavior, the synthesis results require an adaption of the initial test vector set. This reduces the advantage gained by using the automated HLS process. In order to decrease these simulation efforts, in this paper a new method will be presented that enables the usage of the same simulation vectors at both abstraction levels and the execution of an automated simulation comparison.