REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Scheduling and binding algorithms for high-level synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A digit-serial silicon compiler
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Automatic module allocation in high level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Verification by simulation comparison using interface synthesi
Proceedings of the conference on Design, automation and test in Europe
Test scheduling and controller synthesis in the CADDY-system
EURO-DAC '91 Proceedings of the conference on European design automation
CASCH: a scheduling algorithm for "high level"-synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
A scheduling algorithm for optimization and early planning in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Variation-aware resource sharing and binding in behavioral synthesis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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In this paper we present an architectural synthesis system. The system is able to generate multiprocessor architectures from behavioural descriptions. It combines the flexibility of so called high level synthesis systems with the higher throughput rates of DSP synthesis systems.After a short introduction into the CADDY system the impacts of mutual exclusion are briefly discussed. Then a new scheduling algorithm based on delay prediction and a new allocation algorithm based on a graph colouring approach are presented, that take data dependencies in the register assignment into account.